With a performance improvement of an information processing apparatus, a high-speed data rate of a data signal transmitted and received inside and outside of an apparatus has been achieved in recent years. A data signal reception circuit determines an amplitude level of a data signal at timing synchronized with a sampling clock and performs data reproduction based on the determination result. When a high speed data rate is implemented, a slight phase deviation occurring between the data signal and the sampling clock has an influence on an accuracy of data detection. Accordingly, a technology called a tracking CDR (Clock and Data Recovery) which detects the phase deviation and synchronizes a phase of the sampling clock with a phase of the data signal is utilized. The tracking CDR technology includes a technology called a 2× tracking CDR which performs sampling on a 1-bit data twice and a technology called a baud rate tracking CDR which performs sampling on a 1-bit data once.
The baud rate tracking CDR compares the data signal at an adjacent sampling timing with a total of three threshold values, which includes a threshold value for data determination and two threshold values for phase detection, to detect the phase deviation of the sampling clock with respect to the data signal. Therefore, three comparators that compare the data signal with the threshold values are utilized.
Further, an equalization circuit which compensates the received data signal so as to suppress deterioration of a reception sensitivity is used in a reception circuit. As one of equalization circuits, there is a decision feedback equalizer (DFE) which determines whether the output data is 0 (zero) or 1 (one) and feedbacks and uses the determination result so as to suppress amplification of a noise input. Further, there is a speculative DFE adopted as a scheme of achieving a high operational speed of the DFE. The speculative DFE performs an equalization process in advance for all data patterns in a case where the data to be fed back is 0 (zero) or 1 (one). Also, when the data has been fed back, an equalization result corresponding to the data is selected and output. Accordingly, feedback loop processings are reduced and thus the high operational speed of the DFE is implemented. The speculative DFE utilizes a comparator to determine whether data is 0 or 1. When the number of taps is “N”, the number of comparators becomes 2N.
When the baud rate tracking CDR and the speculative DFE described above are utilized in the reception circuit, the number of comparators increases and thus a circuit scale becomes large.
Related techniques are disclosed in, for example, International Publication Pamphlet No. WO 2008/032492, International Publication Pamphlet No. WO 2010/150624, and Japanese Laid-Open Patent Publication No. 2008-301337.